Special Computers Developed at Kobe University

Table of Contents

1 Outline

In 1980's, at the 4th laboratory of the Department of Systems Engineering, Faculty of Engineering, Kobe University, high-performance computers with specialized hardware for high-level languages and parallel computers were actively developed under the supervision of Associate Professor Yukio Kaneda and Professor Sadao Maekawa (department names and titles are at the time). This web page introduces Lisp, Forth, Pascal, and Prolog machines and parallel computers of those.

2 Lisp Machine of Kobe University, FAST LISP

The development of FAST LISP (also known as TAKITAC-7) was started from 1978 and ended on February 1979. It is the first Lisp Machine developed in Japan whose performance was competitive with Lisp systems on main frame computers.

Kazuo Taki (architecture, hardware, and microprogrammed interpreter) and Yasuhiro Kobayashi (frontend processor software) were core developers of this machine.

FAST LISP was certified as an Information Processing Technology Heritage by the Information Processing Society of Japan (Certified date: March 6, 2011). It is displayed at the entrance hall of the Graduate School of System Informatics building from April 2012.

Please refer the web page Lisp Machine of Kobe University, FAST LISP of Information Processing Technology Heritage for details.

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Lisp Machine of Kobe University, FAST LISP
(at the entrance hall of the Graduate School of System Informatics building)

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Certification Plate of Information Processing Technology Heritage

2.2 References

3 Forth and Pascal Machine of Kobe University

Forth and Pascal machine is designed for the high-performance execution of Forth and Pascal languages with a specialized hardware support in about 1982.

Core developers include Koichi Wada (architecture design, hardware, and software) and Toshiyuki Nakatsuji (software).

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Forth and Pascal Machine of Kobe University

4 Prolog Machine of Kobe University, PEK

PEK (Prolog Engine of Kobe University) is an experimental machine developed in 1984 for the high-performance execution of Prolog programs with a specialized hardware support. The hardware of PEK consists of bit slice microprocessor elements comprising a microprogram sequencer and ALU, and specialized hardware circuits for unification and backtracking. These hardware elements can be controlled through horizontal-type microinstructions of 96 bit width, and a Prolog interpreter is implemented as a microprogram. It could perform single inference step within 89 microinstructions, and the execution speed was approximately 60–70K LIPS (Logical Inference Per Second) which was faster than PSI machine developed at ICOT at that time.

Core developers include Naoyuki Tamura (architecture design and software) and Koichi Wada (hardware).

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Prolog Machine of Kobe University, PEK

4.1 References

  • Yukio Kaneda, Naoyuki Tamura, Koichi Wada, Hideo Matsuda, Shumin Kuo, and Sadao Maekawa: Sequential Prolog Machine PEK, New Generation Computing, pp.51–66, 1986.
  • Naoyuki Tamura, Koichi Wada, Hideo Matsuda, Yukio Kaneda, and Sadao Maekawa: Sequential Prolog Machine PEK, Proceedings of the International Conference on Fifth Generation Computer Systems 1984 (FGCS 1984), pp.542–550, 1984.

5 Parallel Computers

Several versions of parallel computers with shared memory were developed. On those machines, parallel numerical computation software and parallel Prolog execution system were implemented.

Core developers include Masaki Kohata (architecture design and hardware), Hideo Matsuda (architecture design and software), and Naoyuki Tamura (software).

5.1 References

  • Naoyuki Tamura and Yukio Kaneda: Implementing Parallel Prolog on a Multi-processor Machine, Proceedings of the 1984 International Symposium on Logic Programming (SLP 1984), pp.42–48, 1984.
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Date: 2012-10-31 11:23:54 JST

Author: Naoyuki Tamura

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